Integrated circuits with two phase-locked loops, or PLLs, are used in reading and writing devices in data-storage disk units.
FIG. 1 shows schematically a system for recovering data coming from a read head of a disk unit. The flow of data to be recovered, indicated by D-IN, is supplied to a data-recovery block D-REC and, by means of a switch SW, to a PLL block, indicated R-PLL, comprising an oscillator OSC-1. The block R-PLL has the function of sampling the flow of data D-IN so as to digitize the analog data coming from the head and thus generate an output sampling signal R-CLK for the data-recovery block D-REC. The digitized data-flow appears at the output D-OUT. Before the start of the data-recovery operation, the block R-PLL is caused to oscillate at a frequency very close to that necessary for reading the track of the disk which contains the data D-IN, by a connection to a terminal, indicated TUN, of a synthesizer block W-PLL, by means of the switch SW. The switch SW is brought from one position to the other alternately at predetermined intervals by suitable timing means TM.
The synthesizer block W-PLL comprises a second PLL with an oscillator OSC-2 which generates, from a constant reference signal FREF, preferably supplied by a quartz oscillator outside the integrated circuit, a certain number of signals of different frequencies amongst which is a timing signal at the terminal TUN, which is used both for writing data on the disk and for the above-described tuning operation.
A problem which arises owing to the presence of the oscillators of the two PLLs in the same integrated circuit is so-called "injection lock" which is due to a coupling between the two oscillators caused by stray currents in the substrate of the integrated circuit and by interference present in the supply voltages of the integrated circuit. In the case described above, when the frequency of the oscillator OSC-1 of the block R-PLL, that is, the reading PLL, is close to that of the signal TUN synthesized by the block W-PLL, the oscillator OSC-1 of the reading PLL R-PLL is locked by the oscillator OSC-2 of the synthesizer block W-PLL, that is, its frequency remains constant when the current for regulating the oscillator varies within a predetermined range around the regulation value corresponding to that frequency. This phenomenon worsens the signal/noise ratio of the system since the input data-flow is sampled at the wrong moments.